Apple’s A20 Pro Doubles the Neural Engine to 32 Cores

On September 9, 2026, Apple announced the A20 Pro — the first smartphone SoC built on a 2-nanometer process, and the first A-series chip to ship a 32-core Neural Engine. Apple describes the design as a “Dual 16-core Neural Engine” delivering double the AI processing power of the A19 Pro, paired with a 50 percent increase in memory bandwidth and GPU-resident Neural Accelerators with 2x faster FP8 math. The chip ships in the iPhone 18 Pro, iPhone 18 Pro Max, and the newly announced iPhone Duo.

Intermediate

Technical Details

The headline number is the Neural Engine. Where the A19 Pro carried 16 NPU cores, the A20 Pro carries 32 — organised, in Apple’s own phrasing, as two 16-core blocks rather than one monolithic 32-core unit. Apple’s floorplan diagram shows them as a visible 8×4 grid occupying the lower-left quadrant of the die.

The rest of the compute budget is split three ways. The CPU stays at six cores — two “supercores” Apple rates at 20 percent faster than the A19 Pro, plus four efficiency cores — with Neural Accelerators integrated into the CPU cores themselves. The GPU grows from six cores to seven, which Apple credits for up to 40 percent faster graphics. And each GPU core now carries its own Neural Accelerator with, per Apple, twice the FP8 throughput of the previous generation.

That gives the A20 Pro three distinct places to run a matrix multiply — CPU accelerators, GPU accelerators, and the Neural Engine proper. Apple has been explicit about the target: 9to5Mac reports the FP8 work is “aimed at advanced AI workloads such as running third-party LLMs on-device.”

Memory Bandwidth Is the Real Story

Apple says the A20 Pro has “the widest memory interface ever shipped in an iPhone,” worth a 50 percent bandwidth increase over the A19 Pro. Apple did not publish either the bus width or a figure in GB/s. Notebookcheck reports, citing pre-launch leaks, a move from a 64-bit to a 96-bit LPDDR5X interface yielding roughly 115 GB/s — arithmetic consistent with a 1.5× multiplier on the A19 Pro, though unconfirmed by Apple.

Apple also borrowed a packaging trick from its desktop silicon: the die now sits side by side with the memory rather than under it, in what Apple calls an M-series-inspired layout. Taking the DRAM out of the SoC’s thermal path lets the silicon bond directly to a redesigned vapor chamber with three times the surface area of the iPhone 17 Pro’s, which Apple credits for up to 40 percent better sustained performance.

What This Means

For local inference, bandwidth matters more than TOPS. Autoregressive decoding is memory-bound: generating each token requires streaming the model’s weights out of DRAM, so tokens per second is capped by bandwidth divided by weight footprint, long before the NPU saturates. A 7B-parameter model quantized to 4 bits occupies roughly 4 GB; at ~115 GB/s that implies a theoretical ceiling near 29 tokens per second, with real throughput lower once activations, KV-cache traffic, and scheduling overhead are counted. The A19 Pro’s narrower bus put that ceiling closer to 19.

Scale is worth keeping in view. The M5 Ultra Mac Studio Apple announced in August moves 1.2 TB/s — roughly ten times the A20 Pro’s reported figure. A phone is not about to run the models a 512 GB desktop runs. What doubling the NPU and widening the bus does buy is headroom for the 1–8B class of quantized models that already run on-device, and for the prefill-heavy workloads — long prompts, document context, computational photography — where compute rather than bandwidth is the binding constraint.

Whether developers can reach that hardware is a separate question. Apple’s Neural Engine has never been directly programmable; third-party code reaches it through Core ML, and researchers have had to reverse-engineer the ANE to do anything else. Apple’s June pledge to open-source the Foundation Models framework and admit third-party models is the more consequential change for anyone wanting to ship an on-device LLM — the A20 Pro supplies the silicon budget, not the access.

Independent benchmarks will settle the rest. Every figure above is a first-party claim; the iPhone 18 Pro ships September 18.

Related Coverage

• Apple’s M5 Ultra Mac Studio: 512GB of Unified Memory for Local AI — the desktop end of the same bandwidth argument, at 1.2 TB/s
• Reverse Engineering Apple’s Neural Engine to Train Transformers on M4 — what it takes to use the ANE outside Core ML
• Apple Open-Sources Its Foundation Models Framework, Adds Claude and Gemini — the software side of on-device third-party models

This post was drafted with AI assistance and reviewed by RITS staff.

Sources

• Apple Newsroom — Apple debuts iPhone 18 Pro and iPhone 18 Pro Max (September 9, 2026)
• Notebookcheck — Apple A20 Pro debuts with 7-core GPU, 32-core Neural Engine and 50% more memory bandwidth
• 9to5Mac — Apple announces A20 Pro chip with 2nm design and major performance gains
• MacRumors — Apple Unveils A20 Pro as First 2nm Smartphone Chip