Alibaba’s RISC-V C950 Runs Qwen3.8-27B at 30 Tokens/s, No GPU

Alibaba’s XuanTie team announced Day-0 support for Qwen3.8-27B on the C950 RISC-V processor on August 18, 2026 — a 27-billion-parameter dense model decoding at more than 30 tokens per second with a 1.9-second time-to-first-token, on CPU cores alone, with no GPU and no binary translation layer. The figures come from a 64-core C950 target configuration, and they are the first credible demonstration that a RISC-V general-purpose core can serve a modern mid-size model at interactive speed.

Advanced

The Chip

Alibaba’s DAMO Academy introduced the XuanTie C950 on March 24, 2026, as licensable 64-bit RISC-V CPU IP rather than a finished part. It is an out-of-order superscalar design compliant with the RVA23 profile: eight-wide instruction decode, a 16-stage pipeline, and a reorder buffer holding more than 1,000 instructions. Clocks reach 3.2 GHz, cores scale to eight per cluster over AMBA CHI.E/CHI.F, and the cache hierarchy offers private L2 from 256 KB to 3 MB with an optional shared L3 of up to 8 MB.

DAMO Academy reported single-core SPECint2006 above 22 points per GHz — roughly 70 at 3.2 GHz — which it described as a record for a RISC-V core and about three times the throughput of its own C920. The Register noted that analysis by a Google researcher placed that single-core figure near Apple’s M1, a part Apple shipped in 2020. Alibaba said the design has been verified on a 5nm process but did not name the foundry; TrendForce reported that sources cited by Nikkei identified TSMC, which Alibaba has not confirmed.

The part that matters for inference is the decoupled matrix block in that diagram. Alongside RISC-V Vector Extension v1.0 and the standard F/D floating-point extensions, the C950 implements XuanTie’s own Attached Matrix Extension (AME v0.5), which attaches a Tensor Processing Engine coprocessor to each core. The Register put each TPE at 8 TOPS, with datatype support running from FP16 down through FP8 and INT4, including the micro-scaling formats MXFP8, MXFP4 and RVFP4. Memory bandwidth is more than four times the C920’s — the constraint that usually decides whether CPU decoding is viable at all.

How the Model Actually Runs

The Day-0 write-up, published by JiWei on August 18, describes the C950 splitting a transformer forward pass across three execution paths on the same silicon: the matrix engine takes the dense GEMMs, the RVV vector units handle normalisation and activation functions, and the scalar cores run control flow and scheduling. Nothing leaves the CPU.

Binding a model graph to those three paths is the job of SHL — Structure of Heterogeneous Library — T-Head’s operator library for XuanTie cores, open-sourced as csi-nn2. SHL selects kernels dynamically according to precision and tensor shape, reorders weights into layouts the matrix unit can stream, preprocesses inputs, reuses buffers, and fuses adjacent operators. It is the same assembly-level optimisation approach T-Head has applied to earlier XuanTie parts such as the C908, extended to the matrix extension.

The same report gives a second data point: Qwen3.8-2.4T-A95B, the 2.4-trillion-parameter Mixture-of-Experts flagship Alibaba open-weighted on August 13, decodes at 7.2 tokens per second with an 8.5-second TTFT on the same configuration. That is not interactive, but it is a 2.4T model running on CPU cores.

What This Means

Two caveats belong up front. First, the numbers are quoted for a “64-core C950 target configuration” — a specification the design is being built toward, not a measurement taken from a shipping 64-core product. The C950 is CPU IP; no commercial 64-core C950 silicon has been announced as available. Second, 30 tokens per second across 64 high-end cores is not competitive with a GPU on either throughput or efficiency, and Alibaba has not claimed otherwise. A single consumer GPU runs the same model several times faster, as the community work on Qwen3.8-27B has demonstrated.

What the result changes is the shape of the deployment question. Qwen3.8-27B fits in 32 GB, which is an ordinary amount of system memory rather than an unusual amount of VRAM. If a general-purpose server CPU with an integrated matrix unit can serve that model at reading speed, then a class of workloads — batch document processing, on-premises agents, edge inference where a discrete accelerator is impractical — stops requiring an accelerator at all. The matrix extension is what makes this different from previous “LLMs on CPU” demonstrations: AME is architectural, not a library trick.

It is also a vertically integrated story in a way few others are. Alibaba designed the instruction set extension, the core, the operator library and the model, and shipped support for its own model on its own core on the day the model was released. T-Head reported 470,000 XuanTie units delivered as of February 2026 against annualised revenue above RMB 10 billion, per TrendForce — a real business, though a small one next to the incumbent CPU vendors. Whether the RISC-V software ecosystem matures fast enough to make that integration matter outside Alibaba’s own stack is the open question, and one this result does not answer.

Related Coverage

• Qwen3.8-27B: Frontier Agentic Scores on a Single Consumer GPU — the model the C950 is running, and its benchmark results
• Qwen3.8-2.4T-A95B: Alibaba Open-Weights Its Max-Tier Flagship — the 2.4T MoE model in the second data point above
• Qwen3.8-Max Preview: Alibaba’s 2.4T-Parameter Bid for the Frontier — earlier coverage of the Max tier

This post was drafted with AI assistance and reviewed by RITS staff.

Sources

• Day 0 适配 | 玄铁 RISC-V 处理器支持 Qwen3.8-27B — JiWei, August 18, 2026 (Chinese)
• Alibaba XuanTie C950 — A powerful, RVA23-compliant 64-bit RISC-V core for Edge AI computing — CNX Software, March 25, 2026
• Alibaba delivers RISC-V server chip optimized for Chinese AI — The Register, March 25, 2026
• Alibaba Unveils RISC-V XuanTie C950 CPU for AI Agents, 5nm Chip Reportedly Made by TSMC — TrendForce, March 25, 2026
• XUANTIE-RV/csi-nn2 — SHL, the XuanTie neural network operator library
• XUANTIE-RV/riscv-matrix-extension-spec — the AME matrix extension proposal